參數(shù)資料
型號(hào): ATTINY26L-8PU
廠商: Atmel
文件頁數(shù): 80/169頁
文件大?。?/td> 0K
描述: IC MCU AVR 2K 5V 8MHZ 20-DIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 18
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 2KB(1K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 612 (CN2011-ZH PDF)
配用: ATSTK600-RC08-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
其它名稱: ATTINY26L-8PJ
ATTINY26L-8PJ-ND
18
1477K–AVR–08/10
ATtiny26(L)
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement mode fea-
tures a 63 address locations reach from the base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data
SRAM in the ATtiny26(L) are all accessible through all these addressing modes.
See “Program and Data Addressing Modes” on page 11 for a detailed description of the different
addressing modes.
EEPROM Data
Memory
The ATtiny26(L) contains 128 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written (see “Memory Programming” on page
107). The EEPROM has an endurance of at least 100,000 write/erase cycles per location.
EEPROM Read/Write
Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time is typically 8.3 ms. A self-timing function lets the user software detect
when the next byte can be written. A special EEPROM Ready Interrupt can be set to trigger
when the EEPROM is ready to accept new data.
An ongoing EEPROM write operation will complete even if a reset condition occurs.
In order to prevent unintentional EEPROM writes, a two state write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed.
EEPROM Address
Register – EEAR
Bit 7 – RES: Reserved Bits
This bit are reserved bit in the ATtiny26(L) and will always read as zero.
Bit 6..0 – EEAR6..0: EEPROM Address
The EEPROM Address Register – EEAR – specifies the EEPROM address in the 128 bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127. The ini-
tial value of EEAR is undefined. A proper value must be written before the EEPROM may be
accessed.
Bit
76543210
$1E ($3E)
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEAR
Read/Write
R
R/W
Initial Value
0
XXXX
XXX
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