參數(shù)資料
型號(hào): ATTINY26L-8PU
廠商: Atmel
文件頁(yè)數(shù): 27/169頁(yè)
文件大小: 0K
描述: IC MCU AVR 2K 5V 8MHZ 20-DIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 18
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 2KB(1K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 612 (CN2011-ZH PDF)
配用: ATSTK600-RC08-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
其它名稱: ATTINY26L-8PJ
ATTINY26L-8PJ-ND
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122
1477K–AVR–08/10
ATtiny26(L)
SPI Serial
Programming
Algorithm
When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK.
When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure
68, Figure 69, and Table 69 for timing details.
To program and verify the ATtiny26 in the serial programming mode, the following sequence is
recommended (See four byte instruction formats in Table 61):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in synchronize the second byte ($53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4
bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 52 on
page 109. The memory page is loaded one byte at a time by supplying the 4 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for given address. The Program Memory Page is stored by loading the Write Pro-
gram Memory Page instruction with the 6 MSB of the address. If polling is not used, the
user must wait at least tWD_FLASH before issuing the next page. (See Table 60). Accessing
the serial programming interface before the Flash write operation completes can result in
incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least tWD_EEPROM before issuing the next byte. (See Table 60). In a chip erased device,
no $FFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the con-
tent at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
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