參數(shù)資料
型號: ATTINY26L-8PU
廠商: Atmel
文件頁數(shù): 158/169頁
文件大小: 0K
描述: IC MCU AVR 2K 5V 8MHZ 20-DIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 18
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 612 (CN2011-ZH PDF)
配用: ATSTK600-RC08-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
其它名稱: ATTINY26L-8PJ
ATTINY26L-8PJ-ND
89
1477K–AVR–08/10
ATtiny26(L)
Figure 48. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps:
1. The a start condition is generated by the master by forcing the SDA low line while the
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the PORTB0 bit to zero. Note that DDRB0 must be set to one for
the output to be enabled. The slave device’s start detector logic (Figure 49.) detects the
start condition and sets the USISIF flag. The flag can generate an interrupt if necessary.
2. In addition, the start detector will hold the SCL line low after the master has forced an
negative edge on this line (B). This allows the slave to wake up from sleep or complete
its other tasks, before setting up the Shift Register to receive the address by clearing the
start condition flag and reset the counter.
3. The master set the first bit to be transferred and releases the SCL line (C). The slave
samples the data and shift it into the serial register at the positive edge of the SCL clock.
4. After eight bits are transferred containing slave address and data direction (read or
write), the slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the master has addressed it releases the SCL line and waits for a new start
condition.
5. If the slave is addressed it holds the SDA line low during the acknowledgment cycle
before holding the SCL line low again (i.e., the Counter Register must be set to 14 before
releasing SCL at (D)). Depending of the R/W bit the master or slave enables its output. If
the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)
The slave can hold the SCL line low after the acknowledge (E).
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given
by the master (F). Or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 49. Start Condition Detector, Logic Diagram
P
S
ADDRESS
1 - 7
8
9
R/W
ACK
1 - 8
9
DATA
ACK
1 - 8
9
DATA
SDA
SCL
A B
D
E
C
F
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR
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