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  • 參數(shù)資料
    型號: ATTINY26L-8PU
    廠商: Atmel
    文件頁數(shù): 106/169頁
    文件大小: 0K
    描述: IC MCU AVR 2K 5V 8MHZ 20-DIP
    產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
    tinyAVR Introduction
    標(biāo)準(zhǔn)包裝: 18
    系列: AVR® ATtiny
    核心處理器: AVR
    芯體尺寸: 8-位
    速度: 8MHz
    連通性: USI
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 16
    程序存儲器容量: 2KB(1K x 16)
    程序存儲器類型: 閃存
    EEPROM 大小: 128 x 8
    RAM 容量: 128 x 8
    電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 20-DIP(0.300",7.62mm)
    包裝: 管件
    產(chǎn)品目錄頁面: 612 (CN2011-ZH PDF)
    配用: ATSTK600-RC08-ND - STK600 ROUTING CARD AVR
    ATSTK600-ND - DEV KIT FOR AVR/AVR32
    ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
    ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
    其它名稱: ATTINY26L-8PJ
    ATTINY26L-8PJ-ND
    41
    1477K–AVR–08/10
    ATtiny26(L)
    I/O Ports
    Introduction
    All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
    This means that the direction of one port pin can be changed without unintentionally changing
    the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
    ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
    input). Each output buffer, except reset, has symmetrical drive characteristics with both high sink
    and source capability. The pin driver is strong enough to drive LED displays directly. All port pins
    have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O
    pins have protection diodes to both VCC and Ground as indicated in Figure 31.
    Figure 31. I/O Pin Equivalent Schematic
    All registers and bit references in this section are written in general form. A lower case “x” repre-
    sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
    when using the register or bit defines in a program, the precise form must be used. For example,
    PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
    ters and bit locations are listed in “Register Description for I/O Ports” on page 56.
    Three I/O memory address locations are allocated for each port, one each for the Data Register
    – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
    I/O location is read only, while the Data Register and the Data Direction Register are read/write.
    In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in
    all ports when set.
    Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
    41. Most port pins are multiplexed with alternate functions for the peripheral features on the
    device. How each alternate function interferes with the port pin is described in “Alternate Port
    Functions” on page 46. Refer to the individual module sections for a full description of the alter-
    nate functions.
    Note that enabling the alternate function of some of the port pins does not affect the use of the
    other pins in the port as general digital I/O.
    Ports as General
    Digital I/O
    The ports are bi-directional I/O ports with optional internal pull-ups. Figure 32 shows a functional
    description of one I/O-port pin, here generically called Pxn.
    C
    pin
    Logic
    R
    pu
    See Figure
    "General Digital I/O" for
    Details
    Pxn
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