參數(shù)資料
型號: ATTINY26L-8PU
廠商: Atmel
文件頁數(shù): 2/169頁
文件大?。?/td> 0K
描述: IC MCU AVR 2K 5V 8MHZ 20-DIP
產(chǎn)品培訓模塊: MCU Product Line Introduction
tinyAVR Introduction
標準包裝: 18
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 612 (CN2011-ZH PDF)
配用: ATSTK600-RC08-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
其它名稱: ATTINY26L-8PJ
ATTINY26L-8PJ-ND
10
1477K–AVR–08/10
ATtiny26(L)
Status Register –
SREG
The AVR Status Register – SREG – at I/O space location $3F is defined as:
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual
interrupt enable control is then performed in the Interrupt Mask Registers – GIMSK and TIMSK.
If the Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled inde-
pendent of the GIMSK and TIMSK values. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also
be set and cleared by the application with the SEI and CLI instructions, as described in the
instruction set reference.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the Instruction
Set Description for detailed information.
Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
Instruction Set Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result after the different arithmetic and logic opera-
tions. See the Instruction Set Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See
the Instruction Set Description for detailed information.
Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit
765
432
1
0
$3F ($5F)
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
Initial Value
0
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ATTINY26L-8SUR 功能描述:8位微控制器 -MCU 2K FL 128B EE 128B SRAM ADC 8MHZ IND 3V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT