參數(shù)資料
型號(hào)： ATMEGA1284-PU
廠商： Atmel
文件頁數(shù)： 98/160頁
文件大?。?/td> 0K
描述： IC MCU AVR 128K FLASH 40PDIP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝： 10
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
42
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
10. Power management and sleep modes
10.1
Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving-
power. The AVR provides various sleep modes allowing the user to tailor the power
consumption to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
10.2
Sleep Modes
Fi gu re 9- 1 on pa ge 3 0 pr ese n ts th e d i ffer e n t clo ck sys tem s in th e At me l
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, and their distribution. The figure is
helpful in selecting an appropriate sleep mode. Table 10-1 shows the different sleep modes,
their wake up sources and BOD disable ability.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which
sleep mode will be activated by the SLEEP instruction. See Table 10-2 on page 47 for a
summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Table 10-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
So
ftw
are
B
O
D
Disdab
le
Sleep Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main
Clo
c
k
So
ur
ce
Enab
led
T
imer
Osc
Enab
led
IN
T2:
0
and
Pin
Chang
e
T
W
IAd
dress
Matc
h
Ti
m
e
r2
SPM/
EEPR
O
M
R
ead
y
AD
C
WD
T
I
n
te
rr
up
t
Oth
e
rI/O
Idle
X
XXXXXXX
ADCNRM
X
XX
XXX
Power-down
X
Power-save
X
XXX
X
Standby(1)
XX
X
Extended
Standby
XX(2)
XXX
X
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