參數(shù)資料
型號： ATMEGA1284-PU
廠商： Atmel
文件頁數(shù)： 51/160頁
文件大?。?/td> 0K
描述： IC MCU AVR 128K FLASH 40PDIP
產(chǎn)品培訓模塊： MCU Product Line Introduction
megaAVR Introduction
標準包裝： 10
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
144
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
17.2.1
Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-
isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag
Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-
tive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clk
T2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and
OC2B). See “Output Compare unit” on page 145 for details. The compare match event will also
set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare
interrupt request.
17.2.2
Definitions
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, that is, TCNT2 for accessing
Timer/Counter2 counter value and so on.
The definitions in Table 17-1 are also used extensively throughout the section.
17.3
Timer/Counter clock sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
T2 is by default equal to the MCU clock, clkI/O. When the AS2
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see ”ASSR
– Asynchronous Status Register” on page 161. For details on clock sources and prescaler, see
Table 17-1.
Definitions.
BOTTOM
The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is depen-
dent on the mode of operation.
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