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參數(shù)資料
型號： ATMEGA1284-PU
廠商： Atmel
文件頁數(shù)： 41/160頁
文件大?。?/td> 0K
描述： IC MCU AVR 128K FLASH 40PDIP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝： 10
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
135
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
16.12.2
TCCRnB – Timer/Counter n Control Register B
Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
Table 16-5.
Waveform Generation mode bit description
Mode
WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter mode of
operation
TOP
Update of
OCRn
x at
TOVn flag
set on
0
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
CTC
OCRnA
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
BOTTOM
TOP
6
0
1
0
Fast PWM, 9-bit
0x01FF
BOTTOM
TOP
7
0
1
Fast PWM, 10-bit
0x03FF
BOTTOM
TOP
8
100
0
PWM, Phase and Frequency
Correct
ICRn
BOTTOM
9
100
1
PWM, Phase and Frequency
Correct
OCRnA
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICRn
TOP
BOTTOM
11
1
0
1
PWM, Phase Correct
OCRnA
TOP
BOTTOM
12
1
0
CTC
ICRn
Immediate
MAX
13
1
0
1
(Reserved)
–
14
1
0
Fast PWM
ICRn
BOTTOM
TOP
15
1
Fast PWM
OCRnA
BOTTOM
TOP
Bit
765
4
3
2
1
0
ICNCn
ICESn
–
WGMn3
WGMn2
CSn2
CSn1
CSn0
TCCRnB
Read/Write
R/W
R
R/W
Initial Value000
0
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