參數(shù)資料
型號： AT91M40807-33AI
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Microcontroller
中文描述： 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 1.40 MM HEIGHT, TQFP-100
文件頁數(shù)： 89/153頁
文件大?。?/td> 1837K
代理商： AT91M40807-33AI
89
AT91X40 Series
1354D
–
ATARM
–
05/02
WD: Watchdog Timer
The AT91X40 Series has an internal watchdog timer which can be used to prevent sys-
tem lock-up if the software becomes trapped in a deadlock. In normal operation the user
reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow
does occur, the watchdog timer generates one or a combination of the following signals,
depending on the parameters in WD_OMR (Overflow Mode Register):
If RSTEN is set, an internal reset is generated (WD_RESET as shown in Figure 35).
If IRQEN is set, a pulse is generated on the signal WDIRQ which is connected to the
Advanced Interrupt Controller
If EXTEN is set, a low level is driven on the NWDOVF signal for a duration of 8 MCK
cycles.
The watchdog timer has a 16-bit down counter. Bits 12-15 of the value loaded when the
watchdog is restarted are programmable using the HPVC parameter in WD_CMR
(Clock Mode). Four clock sources are available to the watchdog counter: MCK/8,
MCK/32, MCK/128 or MCK/1024. The selection is made using the WDCLKS parameter
in WD_CMR. This provides a programmable time-out period of 1 ms to 2 sec. with a 33
MHz system clock.
All write accesses are protected by control access keys to help prevent corruption of the
watchdog should an error condition occur. To update the contents of the mode and con-
trol registers it is necessary to write the correct bit pattern to the control access key bits
at the same time as the control bits are written (the same write access).
Figure 35.
Watchdog Timer Block Diagram
Advanced
Peripheral
Bus (APB)
WD_RESET
WDIRQ
MCKI/8
MCKI/32
MCKI/128
MCKI/1024
Control Logic
Clock Select
16-bit
Programmable
Down Counter
CLK_CNT
Clear
Overflow
NWDOVF
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