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參數(shù)資料
| 型號： | AT91M40807-33AI |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller |
| 中文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 27/153頁 |
| 文件大?。?/td> | 1837K |
| 代理商： | AT91M40807-33AI |
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27
AT91X40 Series
1354D
–
ATARM
–
05/02
Read Protocols
The EBI provides two alternative protocols for external memory read access: standard
and early read. The difference between the two protocols lies in the timing of the NRD
(read cycle) waveform.
The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is
valid for all memory devices. Standard read protocol is the default protocol after reset.
Note:
In the following waveforms and descriptions,
NRD
represents NRD and NOE since the
two signals have the same waveform. Likewise,
NWE
represents NWE, NWR0 and
NWR1 unless NWR0 and NWR1 are otherwise represented.
ADDR
represents A0 - A23
and/or A1 - A23.
Standard Read Protocol
Standard read protocol implements a read cycle in which NRD and NWE are similar.
Both are active during the second half of the clock cycle. The first half of the clock cycle
allows time to ensure completion of the previous access as well as the output of address
and NCS before the read cycle begins.
During a standard read protocol, external memory access, NCS is set low and ADDR is
valid at the beginning of the access while NRD goes low only in the second half of the
master clock cycle to avoid bus conflict (see Figure 14). NWE is the same in both proto-
cols. NWE always goes low in the second half of the master clock cycle (see Figure 15).
Early Read Protocol
Early read protocol provides more time for a read access from the memory by asserting
NRD at the beginning of the clock cycle. In the case of successive read cycles in the
same memory, NRD remains active continuously. Since a read cycle normally limits the
speed of operation of the external memory system, early read protocol can allow a
faster clock frequency to be used. However, an extra wait state is required in some
cases to avoid contentions on the external bus.
Early Read Wait State
In early read protocol, an early read wait state is automatically inserted when an exter-
nal write cycle is followed by a read cycle to allow time for the write cycle to end before
the subsequent read cycle begins (see Figure 16). This wait state is generated in addi-
tion to any other programmed wait states (i.e. data float wait).
No wait state is added when a read cycle is followed by a write cycle, between consecu-
tive accesses of the same type or between external and internal memory accesses.
Early read wait states affect the external bus only. They do not affect internal bus timing.
Figure 14.
Standard Read Protocol
ADDR
NCS
NWE
MCKI
NRD
or
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT91M42800 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M42800-33AI | 功能描述:IC ARM7 MCU 144 TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT91 標準包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT91M42800-33CI | 功能描述:IC ARM7 MCU 144 BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT91 標準包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT91M42800A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M42800A_0203 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
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