參數(shù)資料
型號(hào): AT91M40807-33AI
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Microcontroller
中文描述: 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù): 59/153頁(yè)
文件大小: 1837K
代理商: AT91M40807-33AI
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)當(dāng)前第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
59
AT91X40 Series
1354D
ATARM
05/02
Interrupt Clearing and
Setting
All interrupt sources which are programmed to be edge triggered (including FIQ) can be
individually set or cleared by respectively writing to the registers AIC_ISCR and
AIC_ICCR. This function of the interrupt controller is available for auto-test or software
debug purposes.
Fast Interrupt Request
The external FIQ line is the only source which can raise a fast interrupt request to the
processor. Therefore, it has no priority controller.
The external FIQ line can be programmed to be positive or negative edge triggered or
high- or low-level sensitive in the AIC_SMR0 register.
The fast interrupt handler address can be stored in the AIC_SVR0 register. The value
written into this register is available by reading the AIC_FVR register when an FIQ inter-
rupt is raised. By storing the following instruction at address 0x0000001C, the processor
will load the program counter with the interrupt handler address stored in the AIC_FVR
register.
ldr PC,[PC,# -&F20]
Alternatively the interrupt handler can be stored starting from address 0x0000001C as
described in the ARM7TDMI datasheet.
Software Interrupt
Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be
programmed to be edge triggered in order to set or clear it by writing to the AIC_ISCR
and AIC_ICCR.
This is totally independent of the SWI instruction of the ARM7TDMI processor.
Spurious Interrupt
When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ Mode and the interrupt
handler reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the
core has taken into account the NIRQ assertion and before the read of the IVR.
This behavior is called a Spurious Interrupt.
The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector
when the IVR is read. The Spurious Vector can be programmed by the user when the
vector table is initialized.
A spurious interrupt may occur in the following cases:
With any sources programmed to be level sensitive, if the interrupt signal of the AIC
input is de-asserted at the same time as it is taken into account by the ARM7TDMI.
If an interrupt is asserted at the same time as the software is disabling the
corresponding source through AIC_IDCR (this can happen due to the pipelining of
the ARM core).
The same mechanism of spurious interrupt occurs if the ARM7TDMI reads the IVR
(application software or ICE) when there is no interrupt pending. This mechanism is also
valid for the FIQ interrupts.
Once the AIC enters the spurious interrupt management, it asserts neither the NIRQ nor
the NFIQ lines to the ARM7TDMI as long as the spurious interrupt is not acknowledged.
Therefore, it is mandatory for the Spurious Interrupt Service Routine to acknowledge the
spurious
behavior by writing to the AIC_EOICR (End of Interrupt) before returning to
the interrupted software. It also can perform other operation(s), e.g., trace possible
undesirable behavior.
相關(guān)PDF資料
PDF描述
AT91M42800-33AI AT91 ARM Thumb Microcontrollers
AT91M42800-33CI AT91 ARM Thumb Microcontrollers
AT91M42800A-33AI Single 2-Input Exclusive OR Gate
AT91M42800A-33CI IC LOGIC 1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE -40+85C SC-70-5 3000/REEL
AT91M42800A AT91 ARM Thumb Microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT91M42800 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers
AT91M42800-33AI 功能描述:IC ARM7 MCU 144 TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:AT91 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR,WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB(32K x 8) 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP(0.600",15.24mm) 包裝:管件
AT91M42800-33CI 功能描述:IC ARM7 MCU 144 BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:AT91 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR,WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB(32K x 8) 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP(0.600",15.24mm) 包裝:管件
AT91M42800A 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers
AT91M42800A_0203 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers