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| 型號(hào)： | AT91M40807-33AI |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller |
| 中文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 1.40 MM HEIGHT, TQFP-100 |
| 文件頁(yè)數(shù)： | 73/153頁(yè) |
| 文件大?。?/td> | 1837K |
| 代理商： | AT91M40807-33AI |
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73
AT91X40 Series
1354D
–
ATARM
–
05/02
Fast Interrupt Sequence
It is assumed that:
The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded
with fast interrupt service routine address and the fast interrupt is enabled.
The Instruction at address 0x1C(FIQ exception vector address) is:
ldr pc, [pc, # - &F20].
Nested Fast Interrupts are not needed by the user.
When NFIQ is asserted, if the bit F of CPSR is 0, the sequence is:
1.
The CPSR is stored in SPSR_fiq, the current value of the Program Counter is
loaded in the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded
with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core
adjusts r14_fiq, decrementing it by 4.
2.
The ARM core enters FIQ Mode.
3.
When the instruction loaded at address 0x1C is executed, the Program Counter
is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of
automatically clearing the fast interrupt (source 0 connected to the FIQ line), if it
has been programmed to be edge triggered. In this case only, it de-asserts the
NFIQ line on the processor.
4.
The previous step has effect to branch to the corresponding interrupt service
routine. It is not necessary to save the Link Register(r14_fiq) and the
SPSR(SPSR_fiq) if nested fast interrupts are not needed.
5.
The Interrupt Handler can then proceed as required. It is not necessary to save
registers r8 to r13 because FIQ Mode has its own dedicated registers and the
user r8 to r13 are banked. The other registers, r0 to r7, must be saved before
being used, and restored at the end (before the next step). Note that if the fast
interrupt is programmed to be level sensitive, the source of the interrupt must be
cleared during this phase in order to de-assert the NFIQ line.
6.
Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by
4 (with instruction sub pc, lr, #4 for example). This has effect of returning from the
interrupt to whatever was being executed before, and of loading the CPSR with
the SPSR, masking or unmasking the fast interrupt depending on the state saved
in the SPSR.
Note:
The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just
about to mask FIQ interrupts when the mask instruction was interrupted. Hence when
the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
相關(guān)PDF資料 |
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| AT91M42800-33AI | AT91 ARM Thumb Microcontrollers |
| AT91M42800-33CI | AT91 ARM Thumb Microcontrollers |
| AT91M42800A-33AI | Single 2-Input Exclusive OR Gate |
| AT91M42800A-33CI | IC LOGIC 1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE -40+85C SC-70-5 3000/REEL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT91M42800 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M42800-33AI | 功能描述:IC ARM7 MCU 144 TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT91 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT91M42800-33CI | 功能描述:IC ARM7 MCU 144 BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT91 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT91M42800A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M42800A_0203 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
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