- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381512 > AT91M40807-33AI (ATMEL CORP) Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | AT91M40807-33AI |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller |
| 中文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 105/153頁 |
| 文件大?。?/td> | 1837K |
| 代理商： | AT91M40807-33AI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁當(dāng)前第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁
105
AT91X40 Series
1354D
–
ATARM
–
05/02
Each of these steps can be scheduled by using the interrupt if the bit TXRDY in US_IMR
is set. For character transmission, the USART channel must be enabled before sending
a break.
Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. When
the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. An end of
receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous
Mode or at least one sample in Synchronous Mode. RXBRK is also asserted when an
end of break is detected.
Both the beginning and the end of a break can be detected by interrupt if the bit
US_IMR.RXBRK is set.
Peripheral Data
Controller
Each USART channel is closely connected to a corresponding Peripheral Data Control-
ler channel. One is dedicated to the receiver. The other is dedicated to the transmitter.
Note:
The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR.
The PDC channel is programmed using US_TPR (Transmit Pointer) and US_TCR
(Transmit Counter) for the transmitter and US_RPR (Receive Pointer) and US_RCR
(Receive Counter) for the receiver. The status of the PDC is given in US_CSR by the
ENDTX bit for the transmitter and by the ENDRX bit for the receiver.
The pointer registers (US_TPR and US_RPR) are used to store the address of the
transmit or receive buffers. The counter registers (US_TCR and US_RCR) are used to
store the size of these buffers.
The receiver data transfer is triggered by the RXRDY bit and the transmitter data trans-
fer is triggered by TXRDY. When a transfer is performed, the counter is decremented
and the pointer is incremented. When the counter reaches 0, the status bit is set
(ENDRX for the receiver, ENDTX for the transmitter in US_CSR) which can be pro-
grammed to generate an interrupt. Transfers are then disabled until a new non-zero
counter value is programmed.
Interrupt Generation
Each status bit in US_CSR has a corresponding bit in US_IER (Interrupt Enable) and
US_IDR (Interrupt Disable) which controls the generation of interrupts by asserting the
USART interrupt line connected to the Advanced Interrupt Controller. US_IMR (Interrupt
Mask Register) indicates the status of the corresponding bits.
When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is
asserted.
Channel Modes
The USART can be programmed to operate in three different test modes, using the field
CHMODE in US_MR.
Automatic Echo Mode allows bit by bit re-transmission. When a bit is received on the
RXD line, it is sent to the TXD line. Programming the transmitter has no effect.
Local Loopback Mode allows the transmitted characters to be received. TXD and RXD
pins are not used and the output of the transmitter is internally connected to the input of
the receiver. The RXD pin level has no effect and the TXD pin is held high, as in idle
state.
Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter
and the Receiver are disabled and have no effect. This mode allows bit by bit re-
transmission.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT91M42800-33AI | AT91 ARM Thumb Microcontrollers |
| AT91M42800-33CI | AT91 ARM Thumb Microcontrollers |
| AT91M42800A-33AI | Single 2-Input Exclusive OR Gate |
| AT91M42800A-33CI | IC LOGIC 1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE -40+85C SC-70-5 3000/REEL |
| AT91M42800A | AT91 ARM Thumb Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT91M42800 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M42800-33AI | 功能描述:IC ARM7 MCU 144 TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT91 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT91M42800-33CI | 功能描述:IC ARM7 MCU 144 BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT91 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT91M42800A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M42800A_0203 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。