參數(shù)資料
型號: AT80C51RD2-SLSUM
廠商: Atmel
文件頁數(shù): 78/81頁
文件大?。?/td> 0K
描述: IC 8051 MCU 5V SPI 20MHZ 44-PLCC
標(biāo)準(zhǔn)包裝: 972
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-PLCC
包裝: 管件
8
4113D–8051–01/09
AT80C51RD2
5.
Oscillators
5.1
Overview
One oscillator is available for CPU:
OSC used for high frequency (3 MHz to 40 MHz)
In order to optimize the power consumption and the execution time needed for a specific task,
an internal prescaler feature has been implemented between the selected oscillator and the
CPU.
5.2
Registers
Table 5-1.
Clock Reload Register
Reset Value = 1111 1111b
Not bit addressable
5.2.1
Prescaler Divider
A hardware RESET puts the prescaler divider in the following state:
CKRL = FFh: F
CLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
KS signal selects OSC: F
CLK OUT = FOSC
Any value between FFh down to 00h can be written by software into CKRL register in order to
divide frequency of the selected oscillator:
– CKRL = 00h: minimum frequency
F
CLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
F
CLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)
– CKRL = FFh: maximum frequency
F
CLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
F
CLK CPU = FCLK PERIPH = FOSC (X2 Mode)
–F
CLK CPU and FCLK PERIPH
In X2 mode:
In X1 mode:
765
4321
0
----
Bit
Number
Bit
Mnemonic
Description
7:0
CKRL
Clock Reload Register: Prescaler value
FCPU F
=
CLKPERIPH
FOSC
2
255
CKRL
()
×
----------------------------------------------
=
FCPU F
=
CLKPERIPH
FOSCA
4255
CKRL
()
×
----------------------------------------------
=
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