參數(shù)資料
型號: AT80C51RD2-SLSUM
廠商: Atmel
文件頁數(shù): 48/81頁
文件大?。?/td> 0K
描述: IC 8051 MCU 5V SPI 20MHZ 44-PLCC
標(biāo)準(zhǔn)包裝: 972
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-PLCC
包裝: 管件
52
4113D–8051–01/09
AT80C51RD2
13. Keyboard Interface
The AT80C51RD2 implement a keyboard interface allowing the connection of a 8 x n matrix key-
board. It is based on 8 inputs with programmable interrupt capability on both high or low level.
These inputs are available as alternate function of P1 and allow to exit from idle and power-
down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Key-
board Level Selection register (Table 13-3), KBE, The Keyboard Interrupt Enable register
(Table 13-2), and KBF, the Keyboard Flag register (Table 13-1).
13.0.1
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the same inter-
rupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard
interrupt (see Figure 13-1). As detailed in Figure 13-2 each keyboard input has the capability to
detect a programmable level according to KBLS.x bit value. Level detection is then reported in
interrupt flags KBF.x that can be masked by software using KBE.x bits.
This structure allow keyboard arrangement from 1 x n to 8 x n matrix and allows usage of P1
inputs for other purpose.
Figure 13-1. Keyboard Interface Block Diagram
Figure 13-2. Keyboard Input Circuitry
13.0.2
Power Reduction Mode
P1 inputs allow exit from idle and power-down modes as detailed in Section “Power-down
P1:x
KBE.x
KBF.x
KBLS.x
0
1
VCC
Internal Pull-up
P1.0
Keyboard Interface
Interrupt Request
KBD
IE1
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
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