參數(shù)資料
型號(hào)： AT80C51RD2-SLSUM
廠商： Atmel
文件頁(yè)數(shù)： 33/81頁(yè)
文件大?。?/td> 0K
描述： IC 8051 MCU 5V SPI 20MHZ 44-PLCC
標(biāo)準(zhǔn)包裝： 972
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-PLCC
包裝： 管件
39
4113D–8051–01/09
AT80C51RD2
Table 11-4.
SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
765
4321
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Description
7FE
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM1ModeDescriptionBaud Rate
0
0Shift Registerf
CPU PERIPH/6
1
18-bit UARTVariable
0
29-bit UARTf
CPU PERIPH /32 or /16
1
39-bit UARTVariable
5SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually
mode 1. This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
o transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2=0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop
bit in the other modes.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 11-2. and Figure
11-3. in the other modes.
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