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參數(shù)資料
| 型號(hào)： | AS4LC256K16E0-60JC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K X 16 EDO DRAM, 60 ns, PDSO40 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-40 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 660K |
| 代理商： | AS4LC256K16E0-60JC |
AS4LC256K16EO
2/25/02; V.1.2
Alliance Semiconductor
P. 7 of 24
1RWHV
1ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.
2ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3
An initial pause of 200
s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL (min) ≥ GND and VIH (max) ≤
VCC.
5VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6
Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the spec-
ified tRCD (max) limit, then access time is controlled exclusively by tCAC.
7
Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the spec-
ified tRAD (max) limit, then access time is controlled exclusively by tAA.
8
Assumes three state test load (5 pF and a 380
Thevenin equivalent).
9Either tRCH or tRRH must be satisfied for a read cycle.
10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS
(min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥
tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If nei-
ther of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of tCAA or tCAC or tCAP.
14 tASC ≥ tCP to achieve tPC (min) and tCAP (max) values.
15 These parameters are sampled and not 100% tested.
Key to switching waveform
Read cycle waveform
Undefined/don’t care
Falling input
Rising input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC256K16E0-60TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| AS4LC256K16EO | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO) |
| AS4LC256K16EO-35 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO) |
| AS4LC256K16EO-35TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO) |
| AS4LC256K16EO-45TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO) |
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