參數資料
| 型號： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數： | 82/92頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標準包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應商設備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
82 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
1
RTC_WD
(level)
0
W
Real time clock watchdog interrupt setting
0: disable
1: enable
x
R
Real time clock watchdog interrupt reading
0: RTC o.k.
1: RTC oszillator was stopped, RTC not longer valid
The interrupt gets set in hibernation or during power-up even if
the interrupt is not enabled thus allowing to recognise a
change of the battery connected to BVDDR during hibernation
or shutdown. For a valid reading, the interrupt has to be
enabled first.
0
BVDD_LOW
(level)
0
W
BVDD under-voltage supervisor interrupt setting
0: disable
1: enable
x
R
BVDD supervisor interrupt reading
0: BVDD is above brown out level
1: BVDD has reached brown out level
The threshold can be set in the SUPERVISOR register (21h)
Table 85. Fourth Interrupt Register
Name
Base
Default
IRQENRD_3
2-wire serial
00h
Offset: 26h
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the
corresponding interrupts, while reading gets the actual interrupt status and
will clear the register at the same time. It is not possible to read back the
interrupt enable/disable settings. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
JTEMP_HIGH
(level)
0
W
Supervisor junction over-temperature interrupt setting
0: disable
1: enable
x
R
Supervisor junction over-temperature interrupt reading
0: chip temperature below threshold
1: chip temperature has reached the threshold
The threshold can be set in the SUPERVISOR register (21h)
6
-
0
n/a
Table 84. Thrid Interrupt Register
Name
Base
Default
IRQENRD_2
2-wire serial
00h
Offset: 25h
Third Interrupt Register
Please be aware that writing to this register will enable/disable the
corresponding interrupts, while reading gets the actual interrupt status and
will clear the register at the same time. It is not possible to read back the
interrupt enable/disable settings. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
ams
AG
Technical
content
still
valid
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