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| 型號： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數(shù)： | 22/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
28 - 91
AS3543 3v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by
the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register
byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave.
The word address is incremented internally.
Figure 15. Random Read
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START
condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowl-
edge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmit-
ter. In this state the slave transmits register data located by the previous received word address vector. The master
responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
Figure 16. Sequential Read
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subse-
quently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by
an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the
behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge fol-
lowing the last data byte and generate the STOP condition subsequently.
Figure 17. Current Address Read
To keep the access time as small as possible, this format allows a read access without the word address transfer in
advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read
address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register
byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to
be responded with an acknowledge from the master. For termination of the transmission the master sends a not-
acknowledge following the last data byte and a subsequent STOP condition.
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