參數(shù)資料
型號： AS3543-ECTP
廠商： ams
文件頁數(shù)： 60/92頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO FRONT END 68CTBGA
標(biāo)準(zhǔn)包裝： 4,000
類型： 音頻編解碼器
應(yīng)用： 便攜式音頻，電話
安裝類型： 表面貼裝
封裝/外殼： 68-TFBGA
供應(yīng)商設(shè)備封裝： 68-CTBGA（6x6）
包裝： 帶卷 (TR)
www.austriamicrosystems.com
Revision 1.11
62 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 52. ADC_R Register
Name
Base
Default
ADC_R
2-wire serial
00h
Offset: 10h
Right ADC Input Register
Configures MUX_A and the gain from MUX_A output to the ADC/mixer input (Σ).
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
AVDD27-POR. The register cannot be written when the block is disabled.
Bit
Bit Name
Default
Access
Bit Description
7:6
MUX_A<1:0>
00
R/W
Connect MUX A output to following inputs
00: Microphone (N4/N4)
01: Line_In1 (N1/N8)
10: Line_IN2 (N2/N7)
11: Mixer output (N24/N25)
5
-
0
n/a
4:0
ADR_VOL<4:0>
00000
R/W
volume settings for right ADC input, adjustable in 32 steps @
1.5dB; gain from MUX A output to ADC/mixer input (Σ) (N9)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
Table 53. ADC_L Register
Name
Base
Default
ADC_L
2-wire serial
00h
Offset: 0Fh
Left ADC Input Register
Configures the ADC mode, gain from MUX_A output to the ADC/mixer input (Σ) input
and controls MUTE switch A.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
AVDD27-POR. The register cannot be written when the block is disabled.
Bit
Bit Name
Default
Access
Bit Description
7:6
ADC_MODE<1:0>
00
R/W
Devider setting for ADC sampling frequency
00: I2S LRCK / 2
01: I2S LRCK / 4
10: I2S LRCK
11: I2S LRCK
5
MUTE_A_OFF
0
R/W
Control of MUTE switch A
0: ADC input is set to mute
1: normal operation
4:0
ADL_VOL<4:0>
00000
R/W
volume settings for left ADC input, adjustable in 32 steps @
1.5dB; gain from MUX A output to ADC/mixer input (Σ) (N18)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
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