參數(shù)資料
型號: ARM610
廠商: Mitel Networks Corporation
英文描述: General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器(帶4K字節(jié)緩存,寫緩沖器和存儲器管理單元))
中文描述: 通用32位微處理器4KB的高速緩存,寫緩沖器和存儲器管理單元(通用32位微處理器(帶4K的字節(jié)緩存,寫緩沖器和存儲器管理單元))
文件頁數(shù): 47/174頁
文件大小: 694K
代理商: ARM610
Instruction Set - MRS, MSR
ARM610 Data Sheet
4-19
O
4.5.2 Reserved bits
Only twelve bits of the PSR are defined in ARM610 (N,Z,C,V,I,F, T & M[4:0]); the
remaining bits are reserved for use in future versions of the processor. Refer to
·
Figure 3-6: Program status register formaton page 3-8 for a full description of the
PSR bits.
To ensure the maximum compatibility between ARM610 programs and future
processors, the following rules should be observed:
The reserved bits should be preserved when changing the value in a PSR.
Programs should not rely on specific values from the reserved bits when
checking the PSR status, since they may read as one or zero in future
processors.
A read-modify-write strategy should therefore be used when altering the control bits of
any PSR register; this involves transferring the appropriate PSR register to a general
register using the MRS instruction, changing only the relevant bits and then
transferring the modified value back to the PSR register using the MSR instruction.
Example
The following sequence performs a mode change:
MRS
BIC
ORR
MSR
R0,CPSR
R0,R0,#0x1F
R0,R0,#new_mode
CPSR,R0
; Take a copy of the CPSR.
; Clear the mode bits.
; Select new mode
; Write back the modified
; CPSR.
When the aim is simply to change the condition code flags in a PSR, a value can be
written directly to the flag bits without disturbing the control bits. The following
instruction sets the N,Z,C and V flags:
MSR
CPSR_flg,#0xF0000000
; Set all the flags
; regardless of their
; previous state (does not
; affect any control bits).
No attempt should be made to write an 8-bit immediate value into the whole PSR since
such an operation cannot preserve the reserved bits.
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