參數(shù)資料
型號(hào)： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元））
文件頁數(shù)： 106/174頁
文件大?。?/td> 694K
代理商： ARM610
Memory Management Unit
ARM610 Data Sheet
9-2
9.1
Memory Management Unit (MMU)
The MMU performs two primary functions: it translates virtual addresses into physical
addresses, and it controls memory access permissions. The MMU hardware required
to perform these functions consists of a Translation Look-aside Buffer (TLB), access
control logic, and translation table walking logic.
The MMU supports memory accesses based on Sections or Pages. Sections are
comprised of 1MB blocks of memory. Two different page sizes are supported: Small
Pages consist of 4Kb blocks of memory and Large Pages consist of 64Kb blocks of
memory. (Large Pages are supported to allow mapping of a large region of memory
while using only a single entry in the TLB). Additional access control mechanisms are
extended within Small Pages to 1Kb Sub-Pages and within Large Pages to 16Kb Sub-
Pages.
The MMU also supports the concept of domains—areas of memory that can be
defined to possess individual access rights. The Domain Access Control Register is
used to specify access rights for up to 16 separate domains.
The TLB caches 32 translated entries. During most memory accesses, the TLB
provides the translation information to the access control logic.
If the TLB contains a translated entry for the virtual address, the access control logic
determines whether access is permitted. If access is permitted, the MMU outputs the
appropriate physical address corresponding to the virtual address. If access is not
permitted, the MMU signals the CPU to abort.
If the TLB misses (ie. does not contain a translated entry for the virtual address), the
translation table walk hardware is invoked to retrieve the translation information from
a translation table in physical memory. Once retrieved, the translation information is
placed into the TLB, possibly overwriting an existing value. The entry to be overwritten
is chosen by cycling sequentially through the TLB locations.
When the MMU is turned off (as happens on reset), the virtual address is output
directly onto the physical address bus.
9.2
MMU Program Accessible Registers
The ARM610 Processor provides several 32-bit registers which determine the
operation of the MMU. The format for these registers is shown in
register summary
on page -3. A brief description of the registers is provided below.
Each register will be discussed in more detail within the section that describes its use.
·
Figure 0-1: MMU
Data is written to and read from the MMU's registers using the ARM CPU's MRC and
MCR coprocessor instructions.
相關(guān)PDF資料
PDF描述
ARRAYS NIGHT VISION H.V. RECTIFIER DIODES & ARRAYS
ARS2540 40A GLASS PASSIVATED AVALANCHE BUTTON DIODE
AR2540 40A GLASS PASSIVATED AVALANCHE BUTTON DIODE
ARS25A 25A AUTOMOTIVE BUTTON DIODE
ARS25J 25A AUTOMOTIVE BUTTON DIODE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ARM7-009 制造商:Gravitech 功能描述:ARM7 LPC2378 W/2.8" TCH SCRN LCD BLU
ARM720T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip
ARM7DIMM-LPC2478 功能描述:模塊化系統(tǒng) - SOM LPC2478 ARM7 DIMM Module, Rev 2.2 RoHS:否 制造商:Digi International 外觀尺寸:ConnectCore 9P 處理器類型:ARM926EJ-S 頻率:150 MHz 存儲(chǔ)容量:8 MB, 16 MB 存儲(chǔ)類型:NOR Flash, SDRAM 接口類型:I2C, SPI, UART 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 尺寸:1.97 in x 1.97 in x 6.1 in
ARM7TDI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔
ARM7TDMI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:general purpose 32-bit microprocessors
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*