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| 型號： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元）） |
| 文件頁數(shù)： | 143/174頁 |
| 文件大小： | 694K |
| 代理商： | ARM610 |
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Boundary-Scan Test Interface
ARM610 Data Sheet
11-9
In TEST mode (ie. when either EXTEST or INTEST is the currently selected
instruction), values can be applied to the core logic or output pins independently of the
actual values on the input pins and core logic outputs respectively. On the ARM610,
all of the boundary-scan cells include an update register and thus all of the pins can
be controlled in the above manner. Additional boundary-scan cells are interposed in
the scan chain in order to control the enabling of tristateable buses.
The correspondence between boundary-scan cells and system pins, system direction
controls and system output enables is as shown in
·
Table 11-3: Boundary-scan
signals and pinson page 11-12. The cells are listed in the order in which they are
connected in the boundary-scan register, starting with the cell closest to
TDI
. All
boundary-scan register cells at input pins can apply tests to the on-chip core logic.
The EXTEST guard values specified in
·
Table 11-3: Boundary-scan signals and pins
on page 11-12 should be clocked into the boundary-scan register (using the SAMPLE/
PRELOAD instruction) before the EXTEST instruction is selected, to ensure that
known data is applied to the core logic during the test. The INTEST guard values
shown in the table below should be clocked into the boundary-scan register (using the
SAMPLE/PRELOAD instruction) before the INTEST instruction is selected to ensure
that all outputs are disabled. These guard values should also be used when new
EXTEST or INTEST vectors are clocked into the boundary-scan register.
The values stored in the BS register after power-up are not defined. Similarly, the
values previously clocked into the BS register are not guaranteed to be maintained
across a Boundary-Scan reset (from forcing nTRST LOW or entering the Test Logic
Reset state).
11.7.4 Output Enable Boundary-Scan cells
The boundary-scan register cells Nendout, Nabe, Ntbe, and Nmse control the output
drivers of tristate outputs as shown in the table below. In the case of OUTEN0 enable
cells (Nendout, Ntbe), loading a 1 into the cell will place the associated drivers into the
tristate state, while in the case of type INEN1 enable cells (Nabe, Nmse), loading a 0
into the cell will tristate the associated drivers.
To put all ARM610 tristate outputs into their high impedance state, a logic 1 should be
clocked into the output enable boundary-scan cells Nendout and Ntbe, and a logic 0
should be clocked into Nabe and Nmse. Alternatively, the HIGHZ instruction can be
used.
If the on-chip core logic causes the drivers controlled by Nendout, for example, to be
tristate, (ie. by driving the signal Nendout HIGH), then a 1 will be observed on this cell
if the SAMPLE/PRELOAD or INTEST instructions are active.
11.7.5 Single-step operation
ARM610 is a static design and there is no minimum clock speed. It can therefore be
single-stepped while the INTEST instruction is selected. This can be achieved by
serialising a parallel stimulus and clocking the resulting serial vectors into the
boundary-scan register. When the boundary-scan register is updated, new test stimuli
are applied to the core logic inputs; the effect of these stimuli can then be observed on
the core logic outputs by capturing them in the boundary-scan register.
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