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參數(shù)資料
| 型號： | AM42BDS640AGBC9IS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 8 X 11.60 MM, FBGA-93 |
| 文件頁數(shù)： | 51/72頁 |
| 文件大小： | 1064K |
| 代理商： | AM42BDS640AGBC9IS |
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54
Am42BDS640AG
November 1, 2002
P R E L I M INARY
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. Addresses are latched on the first of either the rising edge
of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in
between programming command sequences.
6. The Synchronous programming operation is independent
of the Set Device Read Mode bit in the Burst Mode
Configuration Register.
7. AVD# must toggle during command sequence unlock cy-
cles.
8. t
AH = 45 ns.
9. CLK must not have an active edge while WE# is at V
IL.
Figure 24.
Alternate Synchronous Program Operation Timings
OE#
CE#f
Data
Addresses
AVD#
WE#
CLK
VCC
555h
PD
tAH
tWC
tWPH
tWP
PA
tVCS
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
tDS
tAVDP
A0h
tACS
tCAS
tACH
tAVCH
tCSW2
tAS
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