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參數(shù)資料
| 型號： | AM42BDS640AGBC9IS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 8 X 11.60 MM, FBGA-93 |
| 文件頁數(shù)： | 29/72頁 |
| 文件大?。?/td> | 1064K |
| 代理商： | AM42BDS640AGBC9IS |
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34
Am42BDS640AG
November 1, 2002
P R E L I M INARY
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a “0” to a “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 s, the system need not monitor DQ3.
See also the Sector Erase Command Sequence sec-
tion.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all
further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the
system software should check the status of DQ3 prior
to and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 16 shows the status of DQ3 relative to the other
status bits.
Table 16.
Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in
non-erase-suspended mode.
Status
DQ7
DQ6
DQ5
DQ3
DQ2
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspend
Mode
Erase-Suspend-
Read (Note 4)
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Non-Erase
Suspended Sector
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
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