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參數(shù)資料
| 型號： | AK4665AEN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20-Bit Stereo CODEC with MIC/HP-AMP |
| 中文描述： | 20位立體聲編解碼器麥克風(fēng)/惠普腺苷 |
| 文件頁數(shù)： | 39/52頁 |
| 文件大小： | 541K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 39 -
5) LIN/RIN/MIN
→
HP-Amp
Power Supply
PDN pin
PMVCM bit
Clock Input
(5)
HPL/R pins
PMHPL/R bits
(8)
Don’t care
HPMTN bit
(1)
>150ns
(3) >0
FS3-0, DFS bits
XH, X
0H, 0
0H, 0
PUT1-0 bits
PTS1-0 bits
XX, XX
00, 00
00, 00
PMCP bit
(6) >0
LINHL, MINHL,
RINHR, MINHR bits
(4) >0
NVSS pin
0V
HVDD
0V
(9)
(11) (12)
Don’t care
HP-Amp State
PD
Normal Operation
PD
MT
MT
(2) >0
(13)
LIN/RIN/MIN pins
(7)
(Hi-Z)
(Hi-Z)
(10)
Figure 25. Power-up/down Sequence of LIN/RIN/MIN and HP-Amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) FS3-0, DFS, PUT1-0 and PTS1-0 bits should be set after PDN pin goes to “H”.
(3) PMVCM bit should be changed to “1” after FS3-0, DFS, PUT1-0 and PTS1-0 bits are set.
(4) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. Each path
is switched-on during the transition time set by FS3-0 and PTS1-0 bits.
(5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit and HP-Amp. External
clocks are also needed for each path (DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits)
setting.
(6) PMCP, PMHPL and PMHPR bits should be changed to “1” after LINHL, MINHL, RINHR and MINHR bits are
changed to “1”. When PMCP bit is changed to “1”, the charge pump circuit is powered-up and NVSS pin goes to
HVDD voltage according to the setting of FS3-0 and DFS bits.
(7) When PMHPL, PMHPR or PMLO bit is changed to “1”, LIN, RIN and MIN pins are biased to VCOM voltage.
Rising time constant is determined by capacitor for AC coupling and input resistance 200k
(typ). In case of
0.047μF input capacitor, time constant is
τ
= 0.047μF x 200k
= 9.4ms (typ)
(8) After power-up the charge pump circuit, HP-Amp is powered-up. Rising time of HP-Amp is determined by
FS3-0,DFS and PUT1-0 bits.
(9) HPMTN bit should be changed to “1” to release the mute after HP-Amp is powered-up. The transition time of mute
release is determined by FS3-0,DFS and PTS1-0 bits.
(10) HPMTN bit should be changed to “0” to mute HP-Amp.
(11) After the transition time for mute, PMHPL and PMHPR bits should be changed to “0” to power-down of HP-Amp.
(12) After power-down of the HP-Amp, PMCP bit should be changed to “0” to power-down of the charge pump circuit.
Falling time constant is determined by external capacitor connected with NVSS pin and internal resistance (typ
17.5k
). In case of 2.2μF capacitor, time constant is
τ
= 2.2μF x 17.5k
= 38.5ms (typ)
(13) Clocks should be stopped after PMCP bit is changed to “0”.
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