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參數(shù)資料
| 型號(hào)： | AK4665AEN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類(lèi)： | Codec |
| 英文描述： | 20-Bit Stereo CODEC with MIC/HP-AMP |
| 中文描述： | 20位立體聲編解碼器麥克風(fēng)/惠普腺苷 |
| 文件頁(yè)數(shù)： | 21/52頁(yè) |
| 文件大小： | 541K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 21 -
3. Example for ALC1 Operation
Table 15 shows the examples of the ALC1 setting.
fs
Register Name Comment
Data
8kHz
16kHz
32kHz
4.1dBFS
Enable
8ms
11.025kHz
22.05kHz
44.1kHz
4.1dBFS
Enable
8.7ms
12kHz
24kHz
48kHz
4.1dBFS
Enable
8ms
LMTH
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
Gain of IVOL
Limiter ATT step
Recovery GAIN step
ALC1 enable
00
0
00
WTM1-0
00
8ms
8.7ms
8ms
REF7-0
IVOL7-0
LMAT1-0
RGAIN1-0
ALC1
E1H
91H
00
00
1
+30dB
0dB
0.375dB
0.375dB
Enable
+30dB
0dB
0.375dB
0.375dB
Enable
+30dB
0dB
0.375dB
0.375dB
Enable
Table 15. Example for the ALC1 setting
The following registers should not be changed during the ALC1 operation. These bits should be changed after the ALC1
operation is finished by ALC1 bit = “0” or PMADC bit = “0”.
- LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Manual Mode
* The value of IVOL should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
WR (REF7-0)
WR (IVOL7-0)
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC1= “1”)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 8ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level =
4.1dBFS
ALC1 bit = “1”
(1) Addr=05H, Data=91H
(2) Addr=02H, Data=00H
(3) Addr=04H, Data=E1H
ALC1 Operation
(4) Addr=03H, Data=20H
Note : WR : Write
Figure 13. Registers set-up sequence at ALC1 operation
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