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參數(shù)資料
| 型號： | AK4665AEN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20-Bit Stereo CODEC with MIC/HP-AMP |
| 中文描述： | 20位立體聲編解碼器麥克風/惠普腺苷 |
| 文件頁數(shù)： | 37/52頁 |
| 文件大?。?/td> | 541K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 37 -
3) DAC
→
HP-Amp
Power Supply
PDN pin
PMVCM bit
Clock Input
(5)
SDTI pin
PMDAC bit
DState
PD
Normal Operation
HPL/R pins
PMHPL/R bits
(7)
ATTL/R7-0 bits
00H(MUTE)
FFH(0dB)
(10) 1061/fs
(9) GD
PD
00H(MUTE)
(9) (10)
Don’t care
HPMTN bit
(1)
>150ns
(3) >0
FS3-0, DFS bits
XH, X
0H, 0
0H, 0
PUT1-0 bits
PTS1-0 bits
XX, XX
00, 00
00, 00
PMCP bit
(6) >0
DACHL bit
DACHR bit
(4) >0
NVSS pin
0V
HVDD
0V
(8)
(12) (13)
Don’t care
HP-Amp State
PD
Normal Operation
PD
MT
MT
(2) >0
(14)
(11)
Figure 23. Power-up/down Sequence of DAC and HP-Amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) FS3-0, DFS, PUT1-0 and PTS1-0 bits should be set after PDN pin goes to “H”.
(3) PMVCM bit should be changed to “1” after FS3-0, DFS, PUT1-0 and PTS1-0 bits are set.
(4) DACHL and DACHR bits should be changed to “1” after PMVCM bit is changed to “1”. Each path is switched-on
during the transition time set by FS3-0 and PTS1-0 bits.
(5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit, HP-Amp or DAC.
External clocks are also needed for each path (DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN
bits) setting.
(6) PMCP, PMDAC, PMHPL and PMHPR bits should be changed to “1” after DACHL and DACHR bits are changed to
“1”. When PMCP bit is changed to “1”, the charge pump circuit is powered-up and NVSS pin goes to
HVDD
voltage according to the setting of FS3-0 and DFS bits
(7) After power-up of the charge pump circuit, HP-Amp is powered-up. Rising time of HP-Amp is determined by FS3-0,
DFS and PUT1-0 bits.
(8) HPMTN bit should be changed to “1” to release the mute after HP-Amp is powered-up. The transition time of mute
release is determined by FS3-0,DFS and PTS1-0 bits.
(9) Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397μs@fs=44.1kHz).
(10) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz).
(11) HPMTN bit should be changed to “0” to mute HP-Amp.
(12) After the transition time for mute, PMDAC, PMHPL and PMHPR bits should be changed to “0” to power-down of
DAC and HP-Amp.
(13) After power-down of the HP-Amp, PMCP bit should be changed to “0” to power-down the charge pump circuit.
Falling time constant is determined by external capacitor connected with NVSS pin and internal resistance (typ
17.5k
). In case of 2.2μF capacitor, time constant is
τ
= 2.2μF x 17.5k
= 38.5ms (typ)
(14) Clocks should be stopped after PMCP bit is changed to “0”.
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