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參數(shù)資料
| 型號(hào)： | AK4665AEN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20-Bit Stereo CODEC with MIC/HP-AMP |
| 中文描述： | 20位立體聲編解碼器麥克風(fēng)/惠普腺苷 |
| 文件頁數(shù)： | 35/52頁 |
| 文件大?。?/td> | 541K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 35 -
Power-Up/Down Sequence
1) ADC (MICIN)
Power Supply
Clock Input
PMADC bit
ADC Internal
State
MICIN pin
PD(Power-down)Init Cycle
Normal Operation
(7) 2081/fs
SDTO pin
(8) GD
(6)
(5)
PD
(8) GD
(Hi-Z)
(Hi-Z)
Don’t care
PMVCM bit
(1) >150ns
(4) >0
FS3-0, DFS bits
(2) >0
(3) >0
Don’t care
PDN pin
XH, X
0H, 0
0H, 0
Figure 21. Power-up/down Sequence of ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) FS3-0 and DFS bits should be set after PDN pin goes to “H”.
(3) PMVCM bit should be changed to “1” after FS3-0 and DFS bits are set.
(4) PMADC bit should be changed to “1” after PMVCM bit is changed to “1”.
(5) External clocks (MCLK, BICK and LRCK) are needed to operate ADC.
(6) When PMADC bit is changed to “1”, MICIN pin is biased to VCOM voltage. Rising time constant is determined by
input capacitor for AC coupling and input resistance. In case of 0.22μF input capacitor, time constant is
τ
= 0.22μF x 30k
= 6.6ms (typ) at MGAIN1 bit = “1”
τ
= 0.22μF x 60k
= 13.2ms (typ) at MGAIN1 bit = “0”
(7) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state.
SDTO is “L” at that time.
(8) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385μs@fs=44.1kHz).
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| AK4666VQ | 功能描述:IC CODEC STEREO 20BIT LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時(shí)間 標(biāo)準(zhǔn)包裝:1,000 |
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| AK4671EG | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/RCV/HP-AMP |
| AK4673 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP and Touch Screen Controller |
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