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參數(shù)資料
| 型號(hào)： | AK4665AEN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20-Bit Stereo CODEC with MIC/HP-AMP |
| 中文描述： | 20位立體聲編解碼器麥克風(fēng)/惠普腺苷 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 541K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 30 -
(3) Example for ALC2 Operation
Table 29 shows the examples of the ALC2 setting. The ALC2 operation starts from 0dB.
fs
Register Name Comment
Data
8kHz
16kHz
32kHz
11.5dBV
500
μ
s
512ms
+12dB
0.5dB
0.5dB
128ms
Enable
11.025kHz
22.05kHz
44.1kHz
11.5dBV
544
μ
s
557ms
+12dB
0.5dB
0.5dB
139ms
Enable
12kHz
24kHz
48kHz
11.5dBV
500
μ
s
512ms
+12dB
0.5dB
0.5dB
128ms
Enable
LMTHP
LTMP1-0
WTMP1-0
REFP7-0
LMATP1-0
RGAINP
PTS1-0
ALC2
Limiter detection Level
Maximum gain at recovery operation
Recovery waiting period
Maximum gain at recovery operation
Limiter ATT Step
Recovery GAIN Step
ALC2 recovery transition time
ALC2 Enable bit
1
10
11
30H
00
0
11
1
Table 29. Example for the ALC2 setting
The following registers should not be changed during the ALC2 operation. These bits should be changed after the ALC2
operation is finished by ALC2 bit is “0” or PMLO bit is “0”.
- LMTHP, LTMP1-0, LMATP1-0, WTMP1-0, RGAINP, REFP5-0, PTS1-0
Example:
ALC2=OFF
WR (LMATP1-0, RGAINP, WTMP1-0)
WR (REFP5-0)
ALC2 Operation
Note : WR : Write
WR (ALC2= “1”)
Limiter Cycle = 544
μ
s @ fs=44.1kHz
Recovery Cycle = 557ms @ fs= 44.1kHz
Limiter and Recovery Step = 1
Maximum Gain = +12dB
Limiter Detection Level =
11.5dBV
Recovery Transition Time = 139ms @ fs=44.1kHz
ALC2 bit = “1”
(1) Addr=12H, Data=18H
(3) Addr=11H, Data=30H
(5) Addr=12H, Data=38H
WR (LMTHP, LTMP1-0)
(2) Addr=13H, Data=18H
WR (PTS1-0)
(4) Addr =14H, Data=C0H
Figure 18. Registers set-up sequence at ALC2 operation
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