
ASAHI KASEI
[AK4588]
MS0287-E-01
2004/03
- 8 -
No.
55
56
57
Pin Name
AVDD
AVSS
RX0
I/O
-
-
I
Function
Analog Power Supply Pin, 4.5V
~
5.5V
Analog Ground Pin, 0V
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 1 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 1 Pin
This pin should be connected to PVSS.
Receiver Channel 2 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 3 Pin (Internal biased pin. Internally biased at PVDD/2)
PLL Ground pin
External Resistor Pin
12k
+/-1% resistor should be connected to PVSS externally.
PLL Power supply Pin, 4.5V
~
5.5V
Receiver Channel 4 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 2 Pin
This pin should be connected to PVSS.
Receiver Channel 5 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 0 Pin (ADC/DAC part)
Receiver Channel 6 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 1 Pin (ADC/DAC part)
Receiver Channel 7 Pin (Internal biased pin. Internally biased at PVDD/2)
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I
2
C Bus
Auxiliary Audio Data Input Pin (DIR/DIT part)
V-bit Input Pin for Transmitter Output
Master Clock Input Pin
Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX2 Data) Output Pin (Default).
Interrupt 0 Pin
58
NC
-
59
RX1
I
60
TEST1
I
61
RX2
I
62
NC
-
63
64
RX3
PVSS
I
-
65
R
-
66
67
PVDD
RX4
-
I
68
TEST2
I
69
70
71
72
73
RX5
CAD0
RX6
CAD1
RX7
I
I
I
I
I
74
I2C
I
75
76
77
78
DAUX2
VIN
MCLK
TX0
I
I
I
O
79
TX1
O
80
INT0
O
Note: All input pins except internal biased pins and internal pull-down pin should not be left floating.
PVDD
VCOM
PVSS
RX pin
20k(typ)
20k(typ)
Internal biased pin Circuit