參數(shù)資料
型號(hào): AK4588
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 2/8 CHANNEL AUDIO CODEC WITH DIR
中文描述: 2 / 8聲道音頻編解碼器迪爾
文件頁數(shù): 67/76頁
文件大?。?/td> 787K
代理商: AK4588
ASAHI KASEI
[AK4588]
MS0287-E-01
2004/03
- 67 -
OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part)
Serial
Control
Interface
AK4588 has two registers, which are ADC/DAC part (AK4628 compatible) and DIR/DIT part (AK4114 compatible).
Each register is set by chip address pin.
(1). 4-wire serial control mode (I2C pin = “L”)
The internal registers may be either written or read by the 4-wire
μ
P interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, ADC/DAC part register is set by CAD1/0 pins. DIR/DIT part C1-0
bits are fixed to “00”), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write
operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read
operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of
CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the
AK4588 should be reset by PDN pin = “L”. Register of ADC/DAC part can not read.
CSN
CDTI
CCLK
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
WRITE
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
C1-C0: Chip Address: (Regarding ADC/DAC part, register is set by CAD1/0
pins. This chip address must be set except “00”.)
(Fixed to “00” for DIR/DIT part)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 40. 4-wire Serial Control I/F Timing
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