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參數(shù)資料
| 型號： | AK4588 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| 中文描述： | 2 / 8聲道音頻編解碼器迪爾 |
| 文件頁數(shù)： | 71/76頁 |
| 文件大?。?/td> | 787K |
| 代理商： | AK4588 |
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ASAHI KASEI
[AK4588]
MS0287-E-01
2004/03
- 71 -
(2)-3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4588.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH
prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The AK4588 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
ADC/DAC part register can not read.
(2)-3-1. CURRENT ADDRESS READ
The AK4588 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1.
After receipt of the slave address with R/W bit set to “1”, the AK4588 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledge to the data but generate the stop condition, the AK4588 discontinues transmission
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n)
Data(n+1)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+2)
Figure 48. CURRENT ADDRESS READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4588 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4588 discontinues
transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
S
S
T
A
R
T
Slave
Address
Word
Address(n)
Slave
Address
A
C
K
Data(n)
A
C
K
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
Figure 49. RANDOM READ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4588VQ | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589VQ | 2/8-Channel Audio CODEC with DIR |
| AK4591 | 24bit 4ch ADC + 24bit 6ch DAC |
| AK4620A | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620AVF | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4588VQ | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589_1 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8-Channel Audio CODEC with DIR |
| AK4589VQ | 制造商:AKM 制造商全稱:AKM 功能描述:2/8-Channel Audio CODEC with DIR |
| AK4591 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit 4ch ADC + 24bit 6ch DAC |
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