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參數(shù)資料
| 型號： | AK4588 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| 中文描述： | 2 / 8聲道音頻編解碼器迪爾 |
| 文件頁數(shù)： | 69/76頁 |
| 文件大?。?/td> | 787K |
| 代理商： | AK4588 |
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ASAHI KASEI
[AK4588]
MS0287-E-01
2004/03
- 69 -
(2)-1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4588 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, the AK4588 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the
STOP condition.
The register of ADC/DAC part can not generate acknowledge for READ operations.
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1
9
8
START
CONDITION
Clock pulse
for acknowledge
not acknowledge
Figure 43. Acknowledge on the I
2
C-bus
(2)-1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If
the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down
the SDA line.
The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device
address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0
pin) set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition is requested by
the master. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
0
0
1
0
0
CAD1
CAD0
R/W
(Regarding ADC/DAC part, register is set by CAD1/0 pins. “00” is inhibited to
set for ADC/DAC.)
(Fixed to “00” for DIR/DIT part)
Figure 44. The First Byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4588VQ | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589VQ | 2/8-Channel Audio CODEC with DIR |
| AK4591 | 24bit 4ch ADC + 24bit 6ch DAC |
| AK4620A | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620AVF | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4588VQ | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589_1 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8-Channel Audio CODEC with DIR |
| AK4589VQ | 制造商:AKM 制造商全稱:AKM 功能描述:2/8-Channel Audio CODEC with DIR |
| AK4591 | 制造商:AKM 制造商全稱:AKM 功能描述:24bit 4ch ADC + 24bit 6ch DAC |
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