參數(shù)資料
型號(hào): AK4537
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP
中文描述: 16位ツヒ立體聲編解碼器與麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 69/76頁
文件大?。?/td> 576K
代理商: AK4537
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 69 -
Stop of Clock
MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”.
1. When X’tal is used in PLL mode
MCKPD bit
(Addr:01H, D7)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:03H, D4)
(1)
(2)
Exam ple :
2
S
Audio I/F Form at : I
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1) Addr:04H, Data:62H
(2) Addr:01H, Data:80H
Figure 57. Stop of Clock Sequence(1)
<Example>
(1) Disable MCKO output : MCKO bit = “1”
“0”
(2) Power down X’tal and PLL, Pull down the XTI pin :
PMXTL bit = PMPLL bit = “1”
“0”, MCKPD = “0”
“1”
2. When an external clock is used in PLL mode
MCKPD bit
(Addr:01H, D7)
External MCLK
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:03H, D4)
Input
(1)
(2)
(3)
Exam ple :
2
S
Audio I/F : I
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1) Addr:04H, Data:62H
(2) Addr:01H, Data:80H
(3) Stop external clock
Figure 58. Stop of Clock Sequence(2)
<Example>
(1) Stop MCKO output : MCKO bit = “1”
“0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1”
“0”, MCKPD = “0”
“1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCLK
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