參數(shù)資料
型號(hào)： AK4537
廠(chǎng)商： Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi)： Codec
英文描述： 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP
中文描述： 16位ツヒ立體聲編解碼器與麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁(yè)數(shù)： 40/76頁(yè)
文件大小： 576K
代理商： AK4537
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 40 -
(2) I
2
C-bus Control Mode (I2C pin = “H”)
The AK4537 supports the standard-mode I
2
C-bus (max: 100kHz). The AK4537 does not support a fast-mode I
2
C-bus
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 36 shows the data transfer sequence for the I
2
C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0
(device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0
pins) set these device address bits (Figure 37). If the slave address matches that of the AK4537, the AK4537 generates an
acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 43). A R/W bit value of “1” indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4537. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 39). The AK4537 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 42).
The AK4537 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4537
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. Only write to address 00H to 10H.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 44) except for the START and STOP
conditions.
SDA
Slave
Address
S
S
T
A
R
T
R/W="0"
A
C
K
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Figure 36. Data Transfer Sequence at the I
2
C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 37. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 38. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 39. Byte Structure after the second byte
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4537VN 制造商:AKM 制造商全稱(chēng):AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP
AK4537VNP-L 制造商:AKM Semiconductor Inc 功能描述:AK4537VNP-L
AK4538 制造商:AKM 制造商全稱(chēng):AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP
AK4538VN 制造商:AKM 制造商全稱(chēng):AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP
AK4541 制造商:AKM 制造商全稱(chēng):AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
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