參數(shù)資料
型號(hào): AK4537
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP
中文描述: 16位ツヒ立體聲編解碼器與麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁(yè)數(shù): 34/76頁(yè)
文件大小: 576K
代理商: AK4537
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 34 -
Speaker Output
The output signal from analog volume is converted into a mono signal [(L+R)/2] and this signal is input to the
Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono BTL output. When DAC output signal is input to MIN
pin as system design example (Figure 47), Speaker-amp can output a maximum of 300mW@SPKG bit = “0” and ALC2
bit = “0” at 8
load when HVDD = 3.3V. When BEEP input is used for DAC output, maximum power becomes 400mW.
Figure 29 and Figure 30 indicates connection examples for 400mW output.
SPKG
ALC2
0
x
0
1
1
Table 20. SPK-Amp Maximum Output Power (x: Don’t care)
Speaker blocks (MOUT2, ALC2 and Speaker-amp) can be powered up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT2, SPP and SPN pins are placed in a Hi-Z state.
When the SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state
and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and
this mode can reduce pop noise at power-up. When the AK4537 is powered down, pop noise can be also reduced by first
entering power-save-mode.
Po(max)
150mW
300mW
250mW
Default
PMSPK bit
SPPS bit
SPP pin
SPN pin
HVDD/2
HVDD/2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 28. Power-up/Power-down Timing for Speaker-amp
[Connection Example for 400mW output]
1)
Using BEEPM pin
16k
MOUT2
0.047u
BEEPM
20k
±
30%
45%AVDD
BPMSP
SPP
SPN
SPK-Amp
AK4537
Figure 29. Connection example for 400mW output using BEEPM pin (SPKG bit = “1”)
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AK4541 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC