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參數(shù)資料
| 型號： | AK4537 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 16位ツヒ立體聲編解碼器與麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 21/76頁 |
| 文件大?。?/td> | 576K |
| 代理商： | AK4537 |
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ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 21 -
System Clock
(1) PLL Mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see
Table.2 and Table.3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table.4
and the MCKO output enable is controlled by the MCKO bit
.
If PS1-0 bits are changed before LRCK is input,
MCKO is not output. PS1-0 bits should be changed after LRCK is input in slave mode.
The PLL should be powered-up after the X’tal oscillator becomes stable or external master clock is inputted. It takes X’tal
oscillator 20ms(typ) to be stable after PMXTL bit=“1”. The PLL needs 40ms lock time, whenever the sampling frequency
changes or the PLL is powered-up (PMPLL bit=“0”
→
“1”).
LRCK and BICK are output from the AK4537 in master mode. When the clock input to MCKI pin stops during normal
operation (PMPLL bit = “1”), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to
“L” (Table 5).
In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized
with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present
whenever the AK4537 is operating (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not
provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “0”).
Mode
PLL1
PLL0
0
0
0
1
0
1
2
1
0
3
1
1
Table 2. MCKI Input Frequency (PLL Mode)
FS2
FS1
FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 3. Sampling Frequency (PLL Mode)
Mode
PS1
PS0
0
0
0
1
0
1
2
1
0
3
1
1
Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)
MCKI
12.288MHz
11.2896MHz
12MHz
N/A
Default
Sampling Frequency
44.1kHz
22.05kHz
11.025kHz
48kHz
32kHz
24kHz
16kHz
8kHz
Default
MCKO
256fs
128fs
64fs
32fs
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4537VN | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4538 | 16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4538VN | 16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4541VQ | AC’97 Rev 2.1 Multimedia Audio CODEC |
| AK4541 | AC’97 Rev 2.1 Multimedia Audio CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4537VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK4537VNP-L |
| AK4538 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4538VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP |
| AK4541 | 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC |
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