參數(shù)資料
型號: AK4537
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP
中文描述: 16位ツヒ立體聲編解碼器與麥克風/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 62/76頁
文件大?。?/td> 576K
代理商: AK4537
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 62 -
Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied.
1. When X'tal is used in PLL mode. (Slave mode)
MCKPD bit
(Addr:01H, D7)
BICK, LRCK
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
XX
00
40ms(max)
Output
Input
(1)
20ms(typ)
(2)
(3)
(4)
(5)
(6)
E xam ple :
A udio I/F Fo rm at : I
2
S
B IC K freq ue ncy at M a ste r M o de : 64fs
Inp ut M aster C lo c k S e lect at P LL M o de : 1 1.2 896M H z
O utp ut M as ter C lo ck F re q ue ncy : 6 4fs
(1) A ddr:01H, D ata:40H
(2) A ddr:01H, D ata:60H
(3) A ddr:04H, D ata 4A H
(4) M CK O output starts
(5) B ICK and LR CK input start
(6) A ddr:04H, D ata 6A H
Figure 49. Clock Set Up Sequence(1)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1”
“0” and power-up the X’tal oscillator: PMXTL bit
= “0”
“1”
(2) Power-up the PLL : PMPLL bit = “0”
“1”
The PLL should be powered-up after the X’tal oscillator becomes stable. It takes X’tal oscillator 20ms(typ) to
be stable after PMXTL bit=“1”. This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0”
“1”.
(3) Enable MCKO output : MCKO bit = “0”
“1”
(4) MCKO is output after PLL becomes stable.
(5) Input BICK and LRCK synchronized with the MCKO output.
(6) Set the MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
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