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參數(shù)資料
| 型號(hào)： | AK4365VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁(yè)數(shù)： | 9/38頁(yè) |
| 文件大小： | 410K |
| 代理商： | AK4365VN |
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ASAHI KASEI
[AK4365]
MS0110-E-01
2003/10
- 9 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD, PLLVCC = 2.7
～
3.3V: C
L
= 20pF)
Parameter
Master Clock Timing
Frequency (EXT= “0”)
(EXT= “1”)
Pulse Width Low (Note 19)
Pulse Width High (Note 19)
AC Pulse Width (Note 23)
LRCK
Frequency
Duty Cycle: Slave Mode
Master Mode
MCKO Output (PLL mode)
Frequency
Duty Cycle (except fs=32kHz, PS1-0= “00”)
(fs=32kHz, PS1-0= “00”)
Serial Interface Timing
(Note 20)
Slave Mode (SMODE = “H”):
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑
” (Note 21)
BICK “
↑
” to LRCK Edge (Note 21)
SDATA Hold Time
SDATA Setup Time
Master Mode (SMODE = “L”):
BICK Frequency (BF = “0”)
(BF = “1”)
BICK Duty
BICK “
↓
” to LRCK
SDATA Hold Time
SDATA Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CS “H” Time
CS “L” Time
CS “
↑
” to CCLK “
↑
”
CCLK “
↑
” to CS “
↑
”
Reset Timing
RSTN Pulse Width (Note 22)
Note 19. Except AC coupling.
Note 20. Refer to “Serial Data Interface”.
Note 21. BICK rising edge must not occur at the same time as LRCK edge.
Note 22. The AK4365 can be reset by bringing RSTN= “L” to “H” only upon power up.
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3.)
Symbol
fCLK
fCLK
tCLKL
tCLKH
tACW
fs
Duty
Duty
fCLKO
dMCK
dMCK
min
11.2896
2.048
0.4/fCLK
0.4/fCLK
20
8
45
typ
max
19.8
12.288
Units
MHz
MHz
ns
ns
ns
kHz
%
%
MHz
%
%
44.1
50
48
55
0.256
40
30
12.288
60
70
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
fBCK
fBCK
dBCK
tMBLR
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSW
tCSS
tCSH
tRST
312.5
100
100
50
50
50
50
-50
50
50
200
80
80
40
40
150
150
150
50
300
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
64fs
32fs
50
50
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