參數(shù)資料
型號(hào)： AK4365VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁(yè)數(shù)： 14/38頁(yè)
文件大?。?/td> 410K
代理商： AK4365VN
ASAHI KASEI
[AK4365]
MS0110-E-01
2003/10
- 14 -
PS1
0
0
1
1
PS0
0
1
0
1
MCKO
256fs
128fs
64fs
32fs
Default
Table 3. MCKO frequency (PLL mode, MCKO bit = “1”)
Master Mode (SMODE = “L”)
Power Up (DAC bit = “1”)
Power Down (DAC bit = “0”)
Refer to Table 1
Don’t care
MCKO pin MCKO bit = “0”: “L”
MCKO bit = “1”: Output
BICK pin
BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
LRCK pin
Output
PLL Unlock
Refer to Table 1
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
“L”
MCKI pin
“L”
“L”
“L”
“L”
Table 4. Clock Operation at Master mode
Slave Mode (SMODE = “H”)
Power Down (DAC bit = “0”)
Don’t care
“L”
Power Up (DAC bit = “1”)
Refer to Table 1
MCKO pin MCKO bit = “0”: “L”
MCKO bit = “1”:Output
BICK pin
Input
LRCK pin
Input
PLL Unlock
Refer to Table 1
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
Input
Input
MCKI pin
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
Table 5. Clock Operation at Slave mode
2) EXT mode (EXT bit = “1”)
The AK4365 can be set to external clock mode (EXT mode) by setting EXT bit (control register: 8FH) to “1”. In EXT
mode, the master clock can be directly input to DAC via MCKI pin without PLL. In this case, the sampling frequency and
MCKI frequency can be selected by FS2-0 bits (refer to Table 6). In EXT mode, PLL2-0 bits are ignored. Table 6 shows
typical sampling frequencies. The sampling frequency can be adjusted from 8kHz to 48kHz by leaving FS2-0 bits fixed
and altering the MCKI frequency. For example, when MCKI=256fs, the sampling frequency can be changed from 8kHz to
48kHz. MCKO output is enabled by controlling MCKO bit. MCKO output frequency can be controlled by PS1-0 bits.
When DAC is powered-up (DAC bit = “1”) from power-down state (DAC bit = “0”), there is a 5ms delay prior to internal
circuit starting up. When changing the sampling frequency during normal operation (DAC bit = “1”), the change of
sampling frequency should occur after the input is muted, or input to “0” data.
LRCK and BICK are output from the AK4365 in master mode. The clock input to MCKI pin should always be present
whenever the AK4365 is in normal operation (DAC bit = “1”). If these clocks are not provided, the AK4365 may draw
excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the AK4365 should be placed in the power-down mode (DAC bit = “0”).
The external clocks required to operate the AK4365 in slave mode are MCKI, LRCK and BICK. The master clock (MCKI)
should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. All external clocks
(MCKI, BICK and LRCK) should always be present whenever the AK4365 is in normal operation mode (DAC bit = “1”).
If these clocks are not provided, the AK4365 may draw excess current and will not operate properly because it utilizes
these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4365 should be placed
in the power-down mode (DAC bit = “0”).
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