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參數(shù)資料
| 型號： | AK4365VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 36/38頁 |
| 文件大小： | 410K |
| 代理商： | AK4365VN |
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ASAHI KASEI
[AK4365]
MS0110-E-01
2003/10
- 36 -
1. Grounding and Power Supply Coupling
The AK4365 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the
analog power supply in the system and DVDD is supplied from AVDD via a 10
resistor. Alternatively if AVDD and
DVDD are supplied separately, the power up sequence is not critical. When AVDD and HPVCC are supplied separately,
AVDD is powered-up at the same time or earlier than HPVCC. When the AK4365 is powered-down, HPVCC is
powered-down at the same time or later than AVDD. The power up sequence of PLLVCC is not critical. AGND, DGND,
PLLGND and HPGND must be connected to the analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as close to the AK4365 as possible, with the small value ceramic capacitors being the nearest.
2. Internal Voltage Reference
Internal voltage reference is output on the VREF pin (typ. 2.0V). An electrolytic capacitor 10
μ
F in parallel with a 0.1
μ
F
ceramic capacitor is attached between VREF and AGND to eliminate the effects of high frequency noise. VCOM is
1.0V(typ) and is a signal ground of this chip. A 1
μ
F electrolytic capacitor in parallel with a 0.1
μ
F ceramic capacitor should
be connected between VCOM and AGND to eliminate the effects of high frequency noise. A ceramic capacitor should be
connected to VCOM pin and located as close as possible to the AK4365. No load current may be drawn from VREF and
VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to avoid
unwanted coupling into the AK4365.
3. Analog Outputs
The analog outputs are single-ended outputs and 1.12Vpp(typ) centered around the VCOM voltage. The input data format
is 2’s compliment. The output voltage is a positive full scale for 7FFFF(@20bit) and negative full scale for
80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). If the noise generated by the delta-sigma
modulator beyond the audio band causes problems, attenuation by an external filter is required.
DC offsets on the analog outputs is eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few
mV.
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