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參數(shù)資料
| 型號： | AK4365VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 33/38頁 |
| 文件大小： | 410K |
| 代理商： | AK4365VN |
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ASAHI KASEI
[AK4365]
MS0110-E-01
2003/10
- 33 -
2) In case of output from LIN, RIN and MIN pins (Full-scale output) to HPL, HPR and MOUT pins (DAC
Power OFF)
DVDD
MOUT bit
HPL,HPR
HPL,HPR pin
MOUT pin
(1)
(3)
(3)
(5)
(2)
(4)
(5)
RSTN pin
AVDD, PLLVCC,
HPVCC
(6)
Figure 25. Power ON/OFF Sequence (2)
(1) Rise time of HP-Amp can be set by a capacitor connected to the MUTET pin. Rise time to 80% is 150ms(min),
300ms(typ) and 600ms(max) when the capacitor is 1
μ
F, and 70ms(min), 140ms(typ) and 290ms(max) when 0.47
μ
F. In
case of 0.47
μ
F, pop noise may be bigger. To rise common voltage, lower side of output signal is clipped.
(2) When HPL and HPR go to HPGND, the power supply of HP-Amp is powered-down.
(3) MOUT bit changes to “1” or “0”, click noise occurs from MOUT pin.
When MOUT bit is “0”, output of MOUT becomes Hi-Z.
(4) After DAC, HPL, HPR and MOUT are powered-down once, it is necessary to wait this amount of time before they are
powered-up once again. (Time required prior to writing to DAC, HPL, HPR and MOUT bits.)
If HPL and HPR bits
are changed to “1” within this time, HP-Amp may not be powered-up.
The time in which HP-Amp is not
powered-up (this partial time is included in the time above) depends on a capacitor connected to the VCOM pin (C
2
),
0.8k x C
2
(max).
(5) Fall time of HP-Amp can be set by a capacitor connected to the MUTET pin. Fall time to 0V is 200ms(min),
400ms(typ) and 860ms(max) when the capacitor is 1
μ
F, and 90ms(min), 190ms(typ) and 410ms(max) when 0.47
μ
F. In
case of 0.47
μ
F, pop noise may be bigger. To fall common voltage, lower side of output signal is clipped.
(6) If only AVDD, PLLVCC and HPVCC are powered ON/OFF when DVDD is powered ON, the RSTN pin should be
changed from “L” to “H” after AVDD, PLLVCC and HPVCC are powered ON.
The time required prior to writing to DAC, HPL, HPR and MOUT bits (4) = Time (1)
For example,
MUTET pin = 1
μ
F, VCOM pin = 10
μ
F
Time (1): max. 860ms
Time (4) = Time (1) = 860ms
For the example above, wait about 860ms writing to DAC, HPL, HPR or MOUT bit.
* If it is necessary to shorten the MUTE sequence time, an external mute circuit should be
implemented. An example of an external mute circuit is shown in the AK4365 evaluation board
manual. The external mute circuit should be released after the HP-Amp is powered up. If the external
mute is released on the way of HP-Amp power-up, large pop noise will occur.
* Power supply of AVDD is powered-up at the same time or earlier than power supply of HPVCC.
Power supply of AVDD is powered-down at the same time or later than power supply of HPVCC.
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