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參數資料
| 型號： | AK4365VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內置的鎖相環(huán) |
| 文件頁數： | 31/38頁 |
| 文件大?。?/td> | 410K |
| 代理商： | AK4365VN |
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ASAHI KASEI
[AK4365]
MS0110-E-01
2003/10
- 31 -
n
Power ON/OFF Sequence
1) In case of DAC output (Full-scale output) to HPL, HPR and MOUT pins (LIN, RIN and MIN: No input)
DVDD
AVDD, PLLVCC,
HPVCC
HPR,MOUT bit
DAC,HPL
<
Case 1>
ATT7-0 bit
HPL,HPR pin
MOUT pin
<Case 2>
ATT7-0 bit
HPL, HPR pin
MOUT pin
(1)
(2
)
(4)
(4)
(2)
(4)
(6)
(2
)
(3)
(1)
00H
FFH
(4)
(6)
(3)
(2
)
00H
FFH
Clock IN
(5)
(6)
(2
)
(6)
(2
)
RSTN pin
(7)
00H
00H
FFH
Figure 24. Power ON/OFF Sequence (1)
(1) Rise time of HP-Amp can be set by a capacitor connected to the MUTET pin. Rise time to 80% is 150ms(min),
300ms(typ) and 600ms(max) when the capacitor is 1
μ
F, and 70ms(min), 140ms(typ) and 290ms(max) when 0.47
μ
F. In
case of 0.47
μ
F, pop noise may be bigger.
(2) ATT7-0 bits are set to 00H on reset. When TM1-0 bits are “00”, the attenuated signal is released by the cycle set by
TM1-0 bits after ATT7-0 bits are set to FFH. (Same as soft mute)
(3) When HPL and HPR go to HPGND, the power supplies to DAC and HP-Amp are powered-down.
(4) When DAC and MOUT bits change to “1” or “0”, click noise occurs from MOUT pin.
When MOUT bit is “0”, output of MOUT becomes Hi-Z.
(5) After DAC, HPL, HPR and MOUT are powered-down once, it is necessary to wait this amount of time before they are
powered-up again. (Time required prior to writing to DAC, HPL, HPR and MOUT bits.)
If HPL and HPR bits are
changed to “1” within this time, HP-Amp may not be powered-up.
The time in which HP-Amp is not
powered-up (this partial time is included in the time above) depends on a capacitor connected to the VCOM pin (C
2
),
0.8k x C
2
(max).
(6) Fall time of HP-Amp can be set by a capacitor connected to the MUTET pin. Fall time to 0V is 200ms(min),
400ms(typ) and 860ms(max) when the capacitor is 1
μ
F, and 90ms(min), 190ms(typ) and 410ms(max) when 0.47
μ
F. In
case of 0.47
μ
F, pop noise may be bigger.
(7) If only AVDD, PLLVCC and HPVCC are powered ON/OFF when DVDD is powered ON, the RSTN pin should be
changed from “L” to “H” after AVDD, PLLVCC and HPVCC are powered ON.
The time required prior to writing to DAC, HPL, HPR and MOUT bits(5) = Time(1) + Soft Mute
Time(2)
For example,
MUTET pin = 1
μ
F, VCOM pin = 1
μ
F, fs = 44.1kHz, Soft mute time setting = 1024/fs (TM1-0 = “00”)
Time (1): max. 860ms
Time (2): max. 23.2ms = 1024/fs + 1/fs @ fs=44.1kHz
Time (5): 883.2ms = 860ms + 23.2ms
For the example above, wait about 883.2ms before writing to DAC, HPL, HPR or MOUT bit.
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