
ASAHI KASEI
[AK4365]
MS0110-E-01
2003/10
- 13 -
OPERATION OVERVIEW
n
System Clock
1) PLL mode (EXT bit = “0”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by PLL2-0 and FS2-0 bits (refer to
Table 1 and Table 2). MCKO output frequency can be controlled by PS1-0 bits (addr=8FH, Table 3). MCKO output can be
enabled by controlling MCKO bit. The lock time of PLL is 20ms from the changing of sampling frequency, and it is also
20ms after a stable MCKI clock is attained after power-up. To decrease output noise from DAC, serial input data is zeroed
internally when PLL is not locked. When DAC is powered-up (DAC bit = “1”) from power-down state (DAC bit = “0”),
there is a 5ms delay before the internal circuit starts up. When changing the sampling frequency during normal operation
(DAC bit = “1”), the change of sampling frequency should occur after the input is muted, or input to “0” data.
LRCK and BICK are output from the AK4365 in master mode. When the clock input to MCKI pin stops during normal
operation (DAC bit = “1”), the internal PLL oscillates (freewheels) at a few MHz, and LRCK and BICK outputs go to “L”
(refer to Table 4).
LRCK input should be synchronized with MCKI or MCKO at slave mode. LRCK and BICK should always be present
whenever the AK4365 is in normal operation mode (DAC bit = “1”). If these clocks are not provided, the AK4365 may
draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers.
If the external clocks are not present, the AK4365 should be placed in the power-down mode (DAC bit = “0”).
Mode
PLL2
PLL1
0
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
7
1
1
Table 1. MCKI Input Frequency (PLL mode)
Mode
FS2
FS1
0
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
7
1
1
Table 2. Sampling Frequency (PLL mode)
PLL0
0
1
0
1
0
1
0
1
MCKI
11.2896MHz
14.4MHz
12MHz
19.2MHz
15.36MHz
13MHz
19.68MHz
19.8MHz
Default
FS0
0
1
0
1
0
1
0
1
fs
Default
48kHz
24kHz
32kHz
16kHz
44.1kHz
22.05kHz
11.025kHz
8kHz