參數(shù)資料
型號(hào)： ADV7312KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat 11-Bit HDTV Video Encoder
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 6/84頁(yè)
文件大?。?/td> 975K
代理商： ADV7312KST
REV. 0
–6–
ADV7312
TIMING SPECIFICATIONS
(V
AA
= 2.375 V–2.625 V, V
DD
= 2.375 V–2.625 V; V
DD_IO
= 2.375 V–3.6 V, V
REF
= 1.235 V, R
SET
= 3040 ,
R
LOAD
= 300 . All specifications T
MIN
to T
MAX
(0 C to 70 C), unless otherwise noted.)
Parameter
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
RESET Low Time
Min
Typ
Max
Unit
Test Conditions
0
0.6
1.3
0.6
0.6
100
400
kHz
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
ns
First clock generated after this period
relevant for repeated start condition
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay
2
Output Skew
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
f
CLK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
111
Data Hold Time, t
121
SD Output Access Time, t
13
SD Output Hold Time, t
14
HD Output Access Time, t
13
HD Output Hold Time, t
14
PIPELINE DELAY
4
7
1
ns
ns
27
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
Progressive scan mode
HDTV mode/async mode
81
40
40
2.0
2.0
15
5.0
14
5.0
63
76
35
41
36
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD [2 , 16 ]
SD component mode [16 ]
PS [1 ]
PS [8 ]
HD [2 , 1 ]
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[7:0]; Y[7:0], S[7:0]
Control:
P_HSYNC
,
P_VSYNC
,
P_BLANK
,
S_HSYNC
,
S_VSYNC
,
S_BLANK
.
4
SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.
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