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參數(shù)資料
| 型號(hào)： | ADV7312KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Multiformat 11-Bit HDTV Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | MS-026BCD, LQFP-64 |
| 文件頁(yè)數(shù)： | 35/84頁(yè) |
| 文件大小： | 975K |
| 代理商： | ADV7312KST |
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REV. 0
ADV7312
–35–
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 14h, Bit 0] from 0 to 1. In this state the horizontal
and vertical counters will remain reset. When this bit is set back
to 0, the internal counters will commence counting again.
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
Table V. Async Timing Mode Truth Table
Reference
in Figure 28
P_HSYNC
P_VSYNC
P_BLANK
*
Reference
1
→
0
0
0
→
1
1
1
0
0
→
1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0
→
1
1
→
0
50% point of falling edge of trilevel horizontal sync signal
25% point of rising edge of trilevel horizontal sync signal
50% point of falling edge of trilevel horizontal sync signal
50% start of active video
50% end of active video
a
b
c
d
e
*
When async timing mode is enabled,
P_BLANK
, Pin 25, becomes an active high input.
P_BLANK
is set to active low at Address 10h, Bit 6.
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