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參數(shù)資料
| 型號(hào)： | ADV7312KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Multiformat 11-Bit HDTV Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 31/84頁 |
| 文件大?。?/td> | 975K |
| 代理商： | ADV7312KST |
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REV. 0
ADV7312
–31–
If in simultaneous SD/HD input mode the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 01h Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
t
DELAY
9.25ns OR
t
DELAY
27.75ns
CLKIN_A
CLKIN_B
Figure 25. Clock Phase with Two Input Clocks
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address[01h] : Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-bit bus and is input
on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is
clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly.
The following figures show the possible conditions: (a) Cb data
on the rising edge and (b) Y data on the rising edge.
3FF
00
00
XY
Y0
Y1
Cr0
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Y7–Y0
Cb0
Figure 26a. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
3FF
00
00
XY
Cb0
Cr0
Y1
CLKIN_B
Y7–Y0
Y0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Figure 26b. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Figure 26c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
Y[7:0]
INTERLACED
TO
PROGRESSIVE
YCrCb
8
3
27MHz OR 54MHz
YCrCb
ADV7312
Figure 27. 1 8-Bit PS at 27 MHz or 54 MHz
Table I provides an overview of all possible input configurations.
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