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參數(shù)資料
| 型號(hào)： | ADV7312KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Multiformat 11-Bit HDTV Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 26/84頁 |
| 文件大?。?/td> | 975K |
| 代理商： | ADV7312KST |
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REV. 0
–26–
ADV7312
LINE 313
LINE 314
LINE 1
t
B
HSYNC
VSYNC
t
A
t
C
Figure 20. Timing Register 1 in PAL Mode
SR7–
SR0
4Ah
Register
SD Timing
Register 0
Bit Description
SD Slave/Master Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Register Setting
Slave Mode
Master Mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No delay
2 clk cycles
4 clk cycles
6 clk cycles
–40 IRE
–7.5 IRE
A low-high-low transition will reset
the internal SD timing counters
Ta = 1 clk cycle
Ta = 4 clk cycles
Ta = 16 clk cycles
Ta = 128 clk cycles
Tb = 0 clk cycle
Tb = 4 clk cycles
Tb = 8 clk cycles
Tb = 18 clk cycles
Tc = Tb
Tc = Tb + 32 s
1 clk cycle
4 clk cycles
16 clk cycles
128 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
Reset
Values
08h
SD Timing Mode
0
0
1
1
0
1
0
1
SD
BLANK
Input
0
1
SD Luma Delay
0
0
1
1
0
1
0
1
SD Min. Luma Value
0
1
0
SD Timing Reset
x
0
0
0
0
0
0
4Bh
SD
HSYNC
Width
0
0
1
1
0
1
0
1
00h
SD
HSYNC
to
VSYNC
Delay
0
0
1
1
0
1
0
1
x
x
0
0
1
1
0
1
0
1
0
1
HSYNC
to Pixel Data Adjust
0
0
1
1
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
4Ch
4Dh
4Eh
4Fh
50h
51h
SD F
SC
Register 0
SD F
SC
Register 1
SD F
SC
Register 2
SD F
SC
Register 3
SD F
SC
Phase
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Pedestal
Register 0
SD Pedestal
Register 1
SD Pedestal
Register 2
SD Pedestal
Register 3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16h
7Ch
F0h
21h
00h
00h
Extended Data on Even Fields
52h
Extended Data on Even Fields
x
x
x
x
x
x
x
x
Extended Data Bit 15–8
00h
53h
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bit 7–0
00h
54h
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bit 15–8
00h
55h
Pedestal on Odd Fields
17
16
15
14
13
12
11
10
00h
56h
Pedestal on Odd Fields
25
24
23
22
21
20
19
18
00h
57h
Pedestal on Even Fields
17
16
15
14
13
12
11
10
00h
58h
Pedestal on Even Fields
25
24
23
22
21
20
19
18
00h
SD Timing
Register 1
Setting any of these bits to 1 will
disable pedestal on the line number
indicated by the bit settings
SD
HSYNC
to
VSYNC
Rising
Edge Delay [Mode 1 Only]
VSYNC Width [Mode 2 Only]
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