參數(shù)資料
型號(hào)： ADV7184
廠商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述： 標(biāo)清多格式視頻解碼器支持快速開(kāi)關(guān)重疊
文件頁(yè)數(shù)： 93/108頁(yè)
文件大?。?/td> 925K
代理商： ADV7184
ADV7184
User Sub Map
Address Register
0x45
Rev. 0 | Page 93 of 108
Bit
Bit Description
CCAPD
7 6 5 4 3 2 1 0 Comments
Notes
These bits are status bits only.
They
cannot
be cleared or
masked. Register 0x46 is used
for this purpose.
0
No CCAPD data detected – VBI
system 2
CCAPD data detected – VBI system 2
Current SD Field is Odd Numbered
Current SD Field is Even Numbered
MPU_STIM_INT = 0
MPU_STIM_INT = 1
Closed captioning not detected in
the input video signal – VBI system 2
Closed captioning data detected in
the video input signal – VBI system 2
Gemstar data not detected in the
input video signal– VBI system 2
Gemstar data detected in the input
video signal– VBI system 2
SD signal has not changed Field
from ODD to Even or Vice versa
SD signal has changed Field from
ODD to Even or Vice versa
Not used
Not used
Manual interrupt not Set
Manual interrupt Set
Do not clear – VBI system 2
Clears CCAPD_Q bit – VBI system 2
Do not clear
Clears GEMD_Q bit
Do not Clear
Clears SD_FIELD_CHNGD_Q bit
Not used
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Masks CCAPD_Q bit – VBI system 2
Unmasks CCAPD_Q bit – VBI system
2
Masks GEMD_Q bit – VBI system 2
Unmasks GEMD_Q bit – VBI system
2
Not used
Masks SD_FIELD_CHNGD_Q bit
Unmasks SD_FIELD_CHNGD_Q bit
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not established
SD vertical sync lock established
SD horizontal sync lock not
established
SD horizontal sync lock established
Not used
SECAM lock not established
SECAM lock established
Not used
Not used
Not used
0
1
x
x
0
1
x
x
x
1
0
Reserved
EVEN_FIELD
Reserved
MPU_STIM_INTRQ
Raw Status 2 (Read Only)
CCAPD_Q
1
0
GEMD_Q
1
Reserved
SD_FIELD_CHNGD_Q
0
x
x
1
Reserved
Reserved
MPU_STIM_INTRQ_Q
0
1
0
1
x
x
x
0
1
x
x
0
1
0
1
0x46
Interrupt Status 2
(Read Only)
These bits can be cleared or
masked by registers 0x47 and
0x48, respectively.
Note that interrupt in register
0x46 for the CCAP, Gemstar,
CGMS and WSS data is using
the Mode 1 data slicer.
x
CCAPD_CLR
GEMD_CLR
Reserved
SD_FIELD_CHNGD_CLR
0
1
Reserved
Reserved
MPU_STIM_INTRQ_CLR
0x47
Interrupt Clear 2
(Write Only)
Note that interrupt in register
0x46 for the CCAP, Gemstar,
CGMS and WSS data is using
the Mode 1 data slicer.
CCAPD_MSKB
0
1
GEMD_MSKB
Reserved
SD_FIELD_CHNGD_MSKB
0
1
0 0
0
1
0 0
0
0
1
0
1
Reserved
MPU_STIM_INTRQ_MSKB
0x48
Interrupt Mask 2
(Read/Write)
Note that interrupt in register
0x46 for the CCAP, Gemstar,
CGMS and WSS data is using
the Mode 1 data slicer.
SD_OP_50Hz. SD 60/50Hz frame rate at
output
SD_V_LOCK
SD_H_LOCK
x
x
x
0
1
x
1
Reserved
SCM_LOCK
Reserved
Reserved
Reserved
0x49
Raw Status 3
(Read Only)
These bits are status bits only.
They
cannot
be cleared or
masked. Register 0x4A is used
for this purpose.
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